1902 search results - page 275 / 381 » Differential Dynamic Logics |
181
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HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
128
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HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
139
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HPCA
2003
IEEE
16 years 3 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
131
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ICCD
2007
IEEE
16 years 8 days ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
155
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WFLP
2009
Springer
15 years 10 months ago
2009
Springer
A logic program strongly terminates if it terminates for any selection rule. Clearly, considering a particular selection rule—like Prolog’s leftmost selection rule—allows one...