787 search results - page 24 / 158 » Digital Algebra and Circuits |
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
ISQED
2010
IEEE
13 years 12 months ago
2010
IEEE
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
DATE
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
TVLSI
2002
13 years 9 months ago
2002
The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brie...
ICCAD
1997
IEEE
14 years 2 months ago
1997
IEEE
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...