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GECCO
2009
Springer
108views Optimization» more  GECCO 2009»
14 years 1 months ago
Development of combinational circuits using non-uniform cellular automata: initial results
A non-uniform cellular automata-based model is presented for the evolutionary development of digital circuits at the gate level. The main feature of this model is the modified lo...
Michal Bidlo, Zdenek Vasícek
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 5 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
ISCAS
2007
IEEE
112views Hardware» more  ISCAS 2007»
14 years 3 months ago
A New Statistical Approach for Glitch Estimation in Combinational Circuits
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
Ahmed Sayed, Hussain Al-Asaad
VLSID
2006
IEEE
87views VLSI» more  VLSID 2006»
14 years 3 months ago
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B...