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HPCA
2007
IEEE
14 years 8 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
HPCA
2005
IEEE
14 years 8 months ago
Unbounded Transactional Memory
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
C. Scott Ananian, Krste Asanovic, Bradley C. Kuszm...
HPCA
2005
IEEE
14 years 8 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
HPCA
2003
IEEE
14 years 8 months ago
TCP: Tag Correlating Prefetchers
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
SACMAT
2009
ACM
14 years 2 months ago
Dynamic mandatory access control for multiple stakeholders
In this paper, we present a mandatory access control system that uses input from multiple stakeholders to compose policies based on runtime information. In the emerging ubiquitous...
Vikhyath Rao, Trent Jaeger