7379 search results - page 1216 / 1476 » Distributed vector architectures |
112
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HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
99
Voted
HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...
131
Voted
HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
177
Voted
HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
124
click to vote
HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
Chip-multiprocessors are becoming the dominant vehicle for general-purpose processing, and parallel software will be needed to effectively utilize them. This parallel software is ...