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» Domain Reduction for the Circuit Constraint
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ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 5 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 4 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
13 years 11 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
ISPD
2004
ACM
120views Hardware» more  ISPD 2004»
14 years 25 days ago
On optimal physical synthesis of sleep transistors
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Changbo Long, Jinjun Xiong, Lei He
DAC
1997
ACM
13 years 11 months ago
An Improved Algorithm for Minimum-Area Retiming
The concept of improving the timing behavior of a circuit by relocating flip-flops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm propose...
Naresh Maheshwari, Sachin S. Sapatnekar