173 search results - page 21 / 35 » Domain Reduction for the Circuit Constraint |
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction....
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
DAC
2003
ACM
14 years 19 days ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...