173 search results - page 5 / 35 » Domain Reduction for the Circuit Constraint |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
CORR
2002
Springer
13 years 7 months ago
2002
Springer
Abstract. Constraint logic programming combines declarativity and efficiency thanks to constraint solvers implemented for specific domains. Value withdrawal explanations have been ...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...