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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 4 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
14 years 5 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
14 years 4 months ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
CODES
2005
IEEE
14 years 4 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 4 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick