46 search results - page 4 / 10 » Drowsy Caches: Simple Techniques for Reducing Leakage Power |
CASES
2008
ACM
13 years 8 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ISLPED
2005
ACM
14 years 8 days ago
2005
ACM
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
HIPEAC
2007
Springer
14 years 26 days ago
2007
Springer
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
EUC
2004
Springer
14 years 3 days ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...