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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
40
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CF
2007
ACM
13 years 9 months ago
Computational and storage power optimizations for the O-GEHL branch predictor
In recent years, highly accurate branch predictors have been proposed primarily for high performance processors. Unfortunately such predictors are extremely energy consuming and i...
Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian
TCSV
2008
128views more  TCSV 2008»
13 years 7 months ago
Compression-Aware Energy Optimization for Video Decoding Systems With Passive Power
The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for configurable platforms to obtain energy savings. DVS is especially attractive for video dec...
Emrah Akyol, Mihaela van der Schaar
JNW
2007
89views more  JNW 2007»
13 years 7 months ago
Traffic Aware Power Saving Protocol in Multi-hop Mobile Ad-Hoc Networks
— This paper presents an optimization of PSM to improve its energy conservation. According to PSM, time is divided into beacon intervals. At the beginning of each beacon interval...
Abdelfattah Belghith, Wafa Akkari, Jean-Marie Bonn...
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu