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» Dynamic Memory Design for Low Data-Retention Power
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PATMOS
2004
Springer
14 years 25 days ago
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems
Portableembeddeddevicesmustpresentlyrunmultimediaandwireless network applications with enormous computational performance requirements at a low energy consumption. In these applica...
David Atienza, Stylianos Mamagkakis, Francky Catth...
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
14 years 8 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
CSREAESA
2003
13 years 8 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 4 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...