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» Dynamic Path Reduction for Software Model Checking
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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 5 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
CODES
2008
IEEE
13 years 10 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
DAC
2008
ACM
14 years 9 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
ICFEM
2009
Springer
14 years 3 months ago
Role-Based Symmetry Reduction of Fault-Tolerant Distributed Protocols with Language Support
Fault-tolerant (FT) distributed protocols (such as group membership, consensus, etc.) represent fundamental building blocks for many practical systems, e.g., the Google File System...
Péter Bokor, Marco Serafini, Neeraj Suri, H...
AOSD
2004
ACM
14 years 2 months ago
Virtual machine support for dynamic join points
A widespread implementation approach for the join point mechanism of aspect-oriented languages is to instrument areas in code that match the static part of pointcut designators, i...
Christoph Bockisch, Michael Haupt, Mira Mezini, Kl...