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DATE
2005
IEEE
112views Hardware» more  DATE 2005»
14 years 3 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
DATE
2002
IEEE
156views Hardware» more  DATE 2002»
14 years 2 months ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy
ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
14 years 6 months ago
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption....
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
DAC
2005
ACM
14 years 10 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 9 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...