157 search results - page 8 / 32 » Dynamic Voltage and Cache Reconfiguration for Low Power |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...