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» Dynamic Voltage and Cache Reconfiguration for Low Power
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HPCA
2005
IEEE
14 years 7 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
13 years 11 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry
ISSS
1999
IEEE
125views Hardware» more  ISSS 1999»
13 years 11 months ago
Real-Time Task Scheduling for a Variable Voltage Processor
This paper presents a real-time task scheduling technique with a variable voltage processor which can vary its supply voltage dynamically. Using such a processor, running tasks wi...
Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
CGO
2005
IEEE
14 years 29 days ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
DSD
2004
IEEE
132views Hardware» more  DSD 2004»
13 years 11 months ago
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...