41 search results - page 5 / 9 » Dynamic fault collapsing and diagnostic test pattern generat... |
ICCAD
1997
IEEE
13 years 12 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
MEMOCODE
2007
IEEE
14 years 2 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
VTS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
In this paper, we propose a diagnostic test generation method in conjunction with an efficient sequential SAT-based diagnosis procedure to precisely identify multiple defective si...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...