41 search results - page 6 / 9 » Dynamic fault collapsing and diagnostic test pattern generat... |
VTS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
1999
IEEE
14 years 11 hour ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ATS
2000
IEEE
14 years 3 days ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...