36 search results - page 5 / 8 » Dynamic performance tuning for speculative threads |
MICRO
1998
IEEE
14 years 1 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
ASPLOS
2010
ACM
14 years 3 months ago
2010
ACM
In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate i...
MICRO
2003
IEEE
14 years 2 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
EUROSYS
2007
ACM
14 years 6 months ago
2007
ACM
In this paper, we extensively tune and then compare the performance of web servers based on three different server architectures. The µserver utilizes an event-driven architectur...