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FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 25 days ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
CAL
2007
13 years 7 months ago
Corollaries to Amdahl's Law for Energy
—This paper studies the important interaction between parallelization and energy consumption in a parallelizable application. Given the ratio of serial and parallel portion in an...
Sangyeun Cho, Rami G. Melhem
HPCA
2005
IEEE
14 years 8 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
HPCC
2007
Springer
14 years 1 months ago
Parallel Genetic Algorithms for DVS Scheduling of Distributed Embedded Systems
Many of today’s embedded systems, such as wireless and portable devices rely heavily on the limited power supply. Therefore, energy efficiency becomes one of the major design con...
Man Lin, Chen Ding