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ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 1 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
14 years 1 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
JPDC
2011
256views more  JPDC 2011»
13 years 3 months ago
Distributed network control for mobile multi-modal wireless sensor networks
A sensor network operates on an infrastructure of sensing, computation, and communication, through which it perceives the evolution of events it observes. We propose a fusion-driv...
Doina Bein, Yicheng Wen, Shashi Phoha, Bharat B. M...
DSN
2009
IEEE
14 years 18 days ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu
DAC
2006
ACM
14 years 9 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang