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CF
2007
ACM
13 years 11 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 1 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
DAC
1999
ACM
13 years 11 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
13 years 11 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
DSN
2008
IEEE
13 years 9 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja