19 search results - page 1 / 4 » Effective Error Diagnosis for RTL Designs in HDLs |
ATS
2002
IEEE
13 years 12 months ago
2002
IEEE
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that ...
VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
ATS
2003
IEEE
14 years 6 days ago
2003
IEEE
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
DATE
2002
IEEE
13 years 12 months ago
2002
IEEE
An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified a...