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» Efficient Design Error Correction of Digital Circuits
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MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 2 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
CSREAESA
2004
13 years 10 months ago
Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
Venkiteswaran Anantharam, Maojiao He, Krishna Nata...
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 3 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
ICCAD
2003
IEEE
193views Hardware» more  ICCAD 2003»
14 years 2 months ago
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
Lei Yang, C.-J. Richard Shi
SIAMSC
2008
140views more  SIAMSC 2008»
13 years 8 months ago
Compact Fourier Analysis for Designing Multigrid Methods
The convergence of Multigrid methods can be analyzed based on a Fourier analysis of the method or by proving certain inequalities that have to be fulfilled by the smoother and by t...
Thomas K. Huckle