303 search results - page 30 / 61 » Efficient Design Error Correction of Digital Circuits |
SLIP
2003
ACM
14 years 2 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit curren...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in ...
ITC
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...