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» Efficient Design Error Correction of Digital Circuits
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ICCD
2004
IEEE
91views Hardware» more  ICCD 2004»
14 years 5 months ago
Diagnosis of Hold Time Defects
In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In...
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han T...
DAC
2004
ACM
14 years 9 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
DAC
2008
ACM
14 years 9 months ago
A progressive-ILP based routing algorithm for cross-referencing biochips
Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated CAD problems have gained much attention, most of which has been devoted to d...
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang...
DAC
2010
ACM
14 years 19 days ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
TCAD
2008
115views more  TCAD 2008»
13 years 8 months ago
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
Javid Jaffari, Mohab Anis