Sciweavers

283 search results - page 28 / 57
» Efficient FPGA hardware development: A multi-language approa...
Sort
View
IPPS
2005
IEEE
14 years 1 months ago
Programming Configurable Multiprocessors
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
Steven A. Guccione
ICRA
2006
IEEE
158views Robotics» more  ICRA 2006»
14 years 1 months ago
An Agent-based Mobile Robot System using Configurable SOC Technique
– To make a mobile robot with real-time vision system adapt to the highly dynamic environments and emergencies under the real-time constraints, a significant account of processin...
Yan Meng
ISCAS
2005
IEEE
99views Hardware» more  ISCAS 2005»
14 years 1 months ago
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...
C. Huggett, K. Maharatna, K. Paul
FPGA
2003
ACM
156views FPGA» more  FPGA 2003»
14 years 27 days ago
Architectures and algorithms for synthesizable embedded programmable logic cores
As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programm...
Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
14 years 9 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...