2620 search results - page 105 / 524 » Efficient Hardware Voxelization |
104
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ICCD
2005
IEEE
16 years 1 months ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
130
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ICCD
2001
IEEE
16 years 1 months ago
2001
IEEE
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
118
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ICCAD
2003
IEEE
16 years 1 months ago
2003
IEEE
Carbon Nanotube Field-Effect Transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators ...
170
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ICCAD
2001
IEEE
16 years 1 months ago
2001
IEEE
- Real-time scheduling on processors that support dynamic voltage and frequency scaling is analyzed. The Slacked Earliest Deadling First (SEDF) algorithm is proposed and it is show...
142
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APCCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...