In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a genera...
In this paper we describe combining a mesh analysis equation formulation technique with a preconditioned GORES matrix solution algorithm to accelerate the determination of inducta...
Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jac...
Most non-trivial applications use some form of input/output (I/O), such as network communication. When model checking such an application, a simple state space exploration scheme i...
Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient c...
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...