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ICCAD
1996
IEEE
114views Hardware» more  ICCAD 1996»
15 years 8 months ago
An efficient approach to simultaneous transistor and interconnect sizing
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
Jason Cong, Lei He
ICCAD
1992
IEEE
153views Hardware» more  ICCAD 1992»
15 years 8 months ago
Efficient techniques for inductance extraction of complex 3-D geometries
In this paper we describe combining a mesh analysis equation formulation technique with a preconditioned GORES matrix solution algorithm to accelerate the determination of inducta...
Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jac...
119
Voted
EUROCAST
2007
Springer
131views Hardware» more  EUROCAST 2007»
15 years 8 months ago
Efficient Model Checking of Applications with Input/Output
Most non-trivial applications use some form of input/output (I/O), such as network communication. When model checking such an application, a simple state space exploration scheme i...
Cyrille Artho, Boris Zweimüller, Armin Biere,...
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
15 years 8 months ago
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocesso
Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient c...
Yiran Chen, Kaushik Roy, Cheng-Kok Koh
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
15 years 8 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...