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134
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FPL
2008
Springer
91views Hardware» more  FPL 2008»
15 years 6 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister
ETS
2009
IEEE
98views Hardware» more  ETS 2009»
15 years 2 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
ICCAD
2009
IEEE
152views Hardware» more  ICCAD 2009»
15 years 2 months ago
Adaptive sampling for efficient failure probability analysis of SRAM cells
In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manip...
Javid Jaffari, Mohab Anis
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
16 years 1 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
153
Voted
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
16 years 1 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...