2620 search results - page 87 / 524 » Efficient Hardware Voxelization |
117
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
- This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The prop...
119
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ATS
2000
IEEE
15 years 8 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
143
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MICRO
2010
IEEE
14 years 11 months ago
2010
IEEE
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
132
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HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
150
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VLSID
2003
IEEE
16 years 4 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...