279 search results - page 16 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
DASC
2006
IEEE
13 years 11 months ago
2006
IEEE
Run-time monitoring is a powerful approach for dynamically detecting faults or malicious activity of software systems. However, there are often two obstacles to the implementation...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
: Future generations of wireless communications are expected to place increasing burdens on the efficiency and linearity of power amplifiers, due to the use of more complex wavefor...