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ASAP
2006
IEEE
168views Hardware» more  ASAP 2006»
13 years 11 months ago
Dual-Processor Design of Energy Efficient Fault-Tolerant System
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
Shaoxiong Hua, Pushkin R. Pari, Gang Qu
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 1 months ago
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Ta...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 11 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
CSSE
2008
IEEE
13 years 9 months ago
A Power-Efficient Floating-Point Co-processor Design
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
Xunying Zhang, Xubang Shen