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IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 26 days ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
JEC
2006
77views more  JEC 2006»
13 years 7 months ago
Tiny split data-caches make big performance impact for embedded applications
This paper shows that even very small data caches, when split to serve data streams exhibiting temporal and spatial localities, can improve performance of embedded applications wit...
Afrin Naz, Krishna M. Kavi, Wentong Li, Philip H. ...
MSS
2007
IEEE
109views Hardware» more  MSS 2007»
14 years 1 months ago
GreenStor: Application-Aided Energy-Efficient Storage
The volume of online data content has shown an un­ precedented growth in recent years. Fueling this growth are new federal regulations which warrant longer data re­ tention and ...
NagaPramod Mandagere, Jim Diehl, David Hung-Chang ...
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 11 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
GLVLSI
2010
IEEE
149views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Lightweight runtime control flow analysis for adaptive loop caching
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
Marisha Rawlins, Ann Gordon-Ross