133 search results - page 6 / 27 » Efficient code caching to improve performance and energy con... |
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
IPPS
2003
IEEE
14 years 26 days ago
2003
IEEE
In this paper we propose mechanisms to improve the performance of parallel Java applications executing on multiprogrammed shared-memory multiprocessors. The proposal is based on a...
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...