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» Efficient hardware code generation for FPGAs
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MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
13 years 5 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
ICCCN
2008
IEEE
14 years 2 months ago
A Structured Hardware/Software Architecture for Embedded Sensor Nodes
—Owing to the limited requirement for sensor processing in early networked sensor nodes, embedded software was generally built around the communication stack. Modern sensor nodes...
Geoff V. Merrett, Alex S. Weddell, Nick R. Harris,...
DAC
2004
ACM
14 years 8 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way...
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
14 years 4 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan