120 search results - page 7 / 24 » Efficient hardware code generation for FPGAs |
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
FPL
2004
Springer
14 years 28 days ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...