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FPL
2007
Springer
97views Hardware» more  FPL 2007»
13 years 11 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
DASFAA
2006
IEEE
174views Database» more  DASFAA 2006»
13 years 11 months ago
Communication-Efficient Implementation of Range-Joins in Sensor Networks
Sensor networks are multi-hop wireless networks of resource constrained sensor nodes used to realize high-level collaborative sensing tasks. To query and access data generated and ...
Aditi Pandit, Himanshu Gupta
OSDI
1994
ACM
13 years 9 months ago
Opportunistic Log: Efficient Installation Reads in a Reliable Storage Server
In a distributed storage system, client caches managed on the basis of small granularity objects can provide better memory utilization then page-based caches. However, object serv...
James O'Toole, Liuba Shrira
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Dynamic code overlay of SDF-modeled programs on low-end embedded systems
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF) –modeled program for low-end embedded systems which lack MMUsupport. With this technique...
Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-m...