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CODES
2005
IEEE
14 years 2 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
VIS
2005
IEEE
128views Visualization» more  VIS 2005»
14 years 10 months ago
Hardware-Accelerated Simulated Radiography
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulatio...
Cláudio T. Silva, Daniel E. Laney, Nelson L...
CODES
1998
IEEE
14 years 1 months ago
The construction of a retargetable simulator for an architecture template
Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, v...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
14 years 1 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
COORDINATION
2008
Springer
13 years 10 months ago
Actors with Multi-headed Message Receive Patterns
Abstract. The actor model provides high-level concurrency abstractions to coordinate simultaneous computations by message passing. Languages implementing the actor model such as Er...
Martin Sulzmann, Edmund S. L. Lam, Peter Van Weert