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GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
14 years 4 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
DAC
2008
ACM
14 years 10 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
SLIP
2005
ACM
14 years 3 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
GECCO
2007
Springer
131views Optimization» more  GECCO 2007»
14 years 3 months ago
Using feedback to regulate gene expression in a developmental control architecture
We present what we believe is the first attempt to physically reconstruct the exploratory mechanism of genetic regulatory networks. Feedback plays a crucial role during developme...
Kester Clegg, Susan Stepney, Tim Clarke