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ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
14 years 4 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
SEUS
2007
IEEE
14 years 1 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
Martin Schlager, Roman Obermaisser, Wilfried Elmen...
ITC
1998
IEEE
94views Hardware» more  ITC 1998»
13 years 11 months ago
Testing embedded-core based system chips
Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from scratch and reuse...
Yervant Zorian, Erik Jan Marinissen, Sujit Dey
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
A novel self-healing methodology for RF Amplifier circuits based on oscillation principles
— This paper proposes a novel self-healing methodology for embedded RF Amplifiers (LNAs) in RF sub-systems. The proposed methodology is based on oscillation principles in which t...
Abhilash Goyal, Madhavan Swaminathan, Abhijit Chat...
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
13 years 11 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...