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INFOCOM
2010
IEEE
13 years 7 months ago
Design and Analysis of a Robust Pipelined Memory System
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
Hao Wang, Haiquan (Chuck) Zhao, Bill Lin, Jun Xu
CODES
2007
IEEE
14 years 2 months ago
Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems
In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded sys...
Paul Pop, Kåre Harbo Poulsen, Viacheslav Izo...
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
14 years 1 months ago
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristic...
Nicola Drago, Franco Fummi, Marco Monguzzi, Giovan...
SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
14 years 1 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
DAC
1999
ACM
14 years 9 months ago
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
Jörg Henkel