395 search results - page 25 / 79 » Encoding Algorithms for Logic Synthesis |
140
Voted
TCAD
2008
15 years 2 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
105
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VTS
1998
IEEE
15 years 6 months ago
1998
IEEE
A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-to...
114
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ICCAD
1999
IEEE
15 years 6 months ago
1999
IEEE
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
115
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ASPDAC
1995
ACM
15 years 6 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
117
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GPCE
2008
Springer
15 years 3 months ago
2008
Springer
A user interface, such as a dialog, assists a user in synthesising a set of values, typically parameters for a command object. Code for “command parameter synthesis” is usuall...