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» Energy minimization using multiple supply voltages
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TVLSI
2002
97views more  TVLSI 2002»
13 years 7 months ago
Techniques for energy-efficient communication pipeline design
The performance of many modern computer and communication systems is dictated by the latency of communication pipelines. At the same time, power/energy consumption is often another...
Gang Qu, Miodrag Potkonjak
CODES
2007
IEEE
13 years 9 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
14 years 2 months ago
Fundamental Data Retention Limits in SRAM Standby Experimental Results
SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
VLSID
2001
IEEE
117views VLSI» more  VLSID 2001»
14 years 8 months ago
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces
Abstract - An adaptive approach for dynamic voltage scheduling on processors is presented based on workload prediction by filtering a trace history. The effects of update frequency...
Amit Sinha, Anantha Chandrakasan
ICCD
2007
IEEE
100views Hardware» more  ICCD 2007»
14 years 4 months ago
VOSCH: Voltage scaled cache hierarchies
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li