Sciweavers

122 search results - page 24 / 25
» Energy reduction in multiprocessor systems using transaction...
Sort
View
JSA
2006
167views more  JSA 2006»
13 years 6 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
14 years 14 days ago
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
Scratch-pad memory is becoming an important fixture in embedded multimedia systems. It is significantly more efficient than the cache, in performance and power, and has the add...
Mohammed Javed Absar, Francky Catthoor
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 14 days ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
IPPS
2007
IEEE
14 years 1 months ago
Load Miss Prediction - Exploiting Power Performance Trade-offs
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
Konrad Malkowski, Greg M. Link, Padma Raghavan, Ma...
EDCC
2008
Springer
13 years 8 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...