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CODES
2006
IEEE
15 years 11 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
IEEEPACT
2008
IEEE
16 years 2 days ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
CASES
2004
ACM
15 years 11 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
CODES
2007
IEEE
16 years 18 hour ago
A data protection unit for NoC-based architectures
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
ISCAS
2006
IEEE
87views Hardware» more  ISCAS 2006»
15 years 11 months ago
NoC monitoring: impact on the design flow
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
Calin Ciordas, Kees Goossens, Andrei Radulescu, Tw...