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» Enhanced leakage reduction Technique by gate replacement
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ICCD
2008
IEEE
498views Hardware» more  ICCD 2008»
14 years 4 months ago
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
Hao Xu, Ranga Vemuri, Wen-Ben Jone
ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
14 years 1 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 7 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
14 years 1 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
DAC
2004
ACM
13 years 11 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...