56 search results - page 6 / 12 » Enhancing test efficiency for delay fault testing using mult... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
ATS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
TOOLS
2000
IEEE
14 years 3 days ago
2000
IEEE
This paper presents a method and a tool for building trustable OO components. The methodology is based on an integrated design and test approach for OO software components. It is ...
ICCAD
1994
IEEE
13 years 12 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...