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» Estimating design time for system circuits
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ISPD
2003
ACM
89views Hardware» more  ISPD 2003»
14 years 1 months ago
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
Andrew B. Kahng, Xu Xu
TASLP
2010
99views more  TASLP 2010»
13 years 6 months ago
A Virtual Model of Spring Reverberation
—The digital emulation of analog audio effects and synthesis components, through the simulation of lumped circuit components has seen a large amount of activity in recent years; ...
Stefan Bilbao, Julian Parker
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 10 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 2 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
FPL
2010
Springer
180views Hardware» more  FPL 2010»
13 years 6 months ago
A Karatsuba-Based Montgomery Multiplier
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip L...