710 search results - page 4 / 142 » Estimating design time for system circuits |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
ISVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing f...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesizehighlyreliablesystems,accurate...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...